On Oct. 14 (local time), at the Open Compute Project (OCP) 2025 Global Summit held at the San Jose Convention Center, Samsung Electronics presented a target pin speed of over 13Gbps for HBM4E, which is under development for 2027. HBM4E has 2,048 pins for data transfer, which translates to 3.25TB/s when converted to bytes (1 byte equals 8 bits). Simultaneously, Samsung Electronics stated that the power efficiency of HBM4E would be more than twice that of the current HBM3E, which is 3.9 picojoules (pJ) per bit.

This is the first time Samsung Electronics has publicly disclosed the target bandwidth for HBM4E since ISSCC 2025 held in San Francisco in January this year. At that time, the company had increased the target bandwidth for HBM4E by 25% compared to last year’s plan, presenting 10Gbps per pin and 2.5TB/s. However, the situation changed in the middle of this year when NVIDIA, the largest consumer of HBM, demanded increased bandwidth for HBM4 to be used in its next-generation AI accelerator “Vera Rubin.”

According to the International Semiconductor Standard Organization (JEDEC) specifications, the bandwidth for HBM4 is 8Gbps per pin, totaling 2TB/s. However, NVIDIA requested over 10Gbps per pin from memory manufacturers Samsung Electronics, SK Hynix, and Micron. In response, Samsung Electronics increased the HBM4 pin speed to 11Gbps, and SK Hynix also succeeded in implementing a corresponding speed. While there were analyses suggesting that Micron was struggling with bandwidth improvement, they recently allayed concerns by announcing in their earnings report that they had delivered HBM4 samples with 11Gbps bandwidth to a “major customer” (NVIDIA).

With the 6th generation HBM4 achieving higher bandwidth than expected even before mass production, the semiconductor industry widely anticipated that the next-generation HBM4E bandwidth would be higher than initially planned. Samsung Electronics’ announcement today not only confirms this prediction but also holds significance as the first among the three memory manufacturers to propose a bandwidth of over 3TB/s. An industry insider said, “Samsung Electronics, which lagged behind competitors in HBM3E, has aimed for higher bandwidth compared to other companies from the early stages of HBM4 development,” adding, “As the ‘speed race’ in HBM4 is nearing success, they are moving quickly in the next generation to aim for a reversal in strategy.”

Samsung Electronics also introduced the specific specifications of its initial LPDDR6 product, the next-generation mobile DRAM whose JEDEC standard was released in July. The plan is to achieve a bandwidth of 114.1 gigabytes per second (GB/s) with 10.7Gbps per pin while improving power efficiency by 20% compared to the existing LPDDR5X.