In an academic conference held in Suwon, South Korea, SK Hynix researcher Seo Jae-Wook revealed that the company is evaluating the shift from the current 6F2 DRAM manufacturing process to a more cost-effective alternative. The increase in EUV lithography costs from the 1c DRAM generation has prompted the company to explore the feasibility of producing DRAM through alternative methods.

Seo Jae-Wook highlighted the potential of VG (Vertical Gate) or 3D DRAM as a solution, referring to a new type of memory that builds cell structures vertically, also known as 4F2 DRAM. Samsung Electronics has previously introduced a similar technology under the name VCT (Vertical Channel Transistor) DRAM. This innovative structure places the source, gate, drain, and capacitor vertically, connecting word lines and bit lines to the gate and source, respectively. This design could reduce the chip area by approximately 30% compared to the existing 6F2 DRAM process.

The 4F2 DRAM is anticipated to enter mass production after the 0a nm node, which Seo Jae-Wook estimates will occur following the 1c nm DRAM generation that is set to be released between 2024 and 2025 by the major manufacturers, including Samsung Electronics, SK Hynix, and Micron.

The introduction of the next 1d nm node is expected to employ EUV multi-patterning, significantly increasing the cost of the EUV lithography phase in the production process. Utilizing VG or 3D DRAM structures could potentially reduce the EUV lithography cost for memory to less than half of that for traditional 6F2 DRAM. While the VG DRAM could maintain lower lithography costs for 1 to 2 generations, the EUV cost is expected to rise sharply afterward. On the other hand, the 3D DRAM approach would necessitate substantial investment in deposition and etching equipment.

As the memory industry continues to grapple with the balance between technological advancement and cost efficiency, SK Hynix's strategic considerations underscore the ongoing challenges and innovations within the semiconductor market.