JEDEC, the global leader in microelectronics industry standards, has proudly announced its upcoming standards for advanced memory modules that will power the next generation of high-performance computing and AI applications. The association has revealed key details about its upcoming DDR5 MRDIMM and next-generation LPDDR6 CAMM standards, which are expected to revolutionize the industry with unprecedented bandwidth and memory capacity.

DDR5 MRDIMMs offer an innovative module design that enhances data transfer rates and overall system performance. The multiplexing feature allows for the combination of multiple data signals over a single channel, effectively increasing bandwidth without additional physical connections. This seamless bandwidth upgrade enables applications to exceed DDR5 RDIMM data rates. Other planned features include platform compatibility with RDIMM for flexible end-user bandwidth configuration, utilization of standard DDR5 DIMM components, efficient I/O scaling, and support for multi-generational scaling to DDR5-EOL.

The JEDEC MRDIMM standard is expected to deliver up to twice the peak bandwidth of native DRAM, enabling applications to surpass current data rates and achieve new levels of performance. It maintains the same capacity, reliability, availability, and serviceability (RAS) features as JEDEC RDIMM. The committee aims to double the bandwidth to 12.8 Gbps and increase the pin speed. The MRDIMM is designed to support more than two ranks and is envisioned to utilize standard DDR5 DIMM components, ensuring compatibility with conventional RDIMM systems.

Furthermore, JEDEC is developing a Tall MRDIMM form factor to offer higher bandwidth and capacity without changes to the DRAM package. This innovative form factor will allow for twice the number of DRAM single-die packages to be mounted on the DIMM without the need for 3DS packaging.

Building on JEDEC’s JESD318 CAMM2 Memory Module standard, the JC-45 Committee is developing a next-generation CAMM module for LPDDR6, targeting a maximum speed greater than 14.4 GT/s. The module is planned to offer a 24-bit subchannel, a 48-bit channel, and a connector array.

Both projects are in active development within JEDEC’s JC-45 Committee for DRAM Modules. JEDEC encourages companies to join and contribute to the development of future standards. Membership provides access to pre-publication proposals and early insights into projects like MRDIMM.

It is important to note that JEDEC standards are subject to change during and after the development process, including the possibility of disapproval by the JEDEC Board of Directors.