In a recent development reported by The Korea Economic Daily, SK Hynix has chosen to use Taiwan Semiconductor Manufacturing Company's (TSMC) N5 process foundation die for its upcoming HBM4 memory. This decision comes as the Joint Electron Device Engineering Council (JEDEC) solidifies the standards for the new generation of HBM memory, with the first HBM4 products from SK Hynix expected to hit the market in the latter half of 2025.

This strategic alliance was confirmed in April when both SK Hynix and TSMC signed a memorandum of understanding to strengthen their cooperation on the foundation die for HBM memory. TSMC showcased two versions of the HBM4 memory foundation die at its 2024 European Technology Symposium: the N12FFC+ version aimed at price-sensitive products and the N5 version designed for high-performance applications.

The N5 version stands out with a die area that is only 39% of the N12FFC+ version, achieving a logic circuit frequency of up to 155% of the N12FFC+ version under the same power conditions, with power consumption at just 35% of the latter at the same frequency. The N5 foundation die enables interconnect spacing at the 6~9μm level and, in addition to the prevalent 2.5D packaging integration, supports 3D vertical integration of HBM4 memory with logic processors. This vertical structure promises to deliver substantial memory bandwidth, potentially revolutionizing the HPC & AI chip landscape.

The transition of HBM memory foundation die production to a logic wafer foundry like TSMC is a testament to the convergence of two major semiconductor manufacturing domains. Reports from Korean media suggest that both SK Hynix and Samsung Electronics are bolstering their HBM memory teams with additional logic design talent, indicating a significant push towards integrating advanced memory solutions with cutting-edge logic processing capabilities.