According to reports from South Korean media and industry insiders, Samsung Electronics is gearing up to launch its three-dimensional (3D) packaging service for high bandwidth memory (HBM) chips within this year. This new service is anticipated to be instrumental in the development of the HBM4 generation, slated for release in 2025.

Samsung has recently unveiled its latest chip packaging technology and service roadmap, marking the first time the company has publicly disclosed its 3D packaging technology for HBM chips. Traditionally, HBM chips have been packaged using 2.5D technology.

The innovative packaging technique from Samsung involves vertically stacking the HBM chips on top of the GPU, which is expected to enhance data learning and inference processing speeds. This technology is poised to be a game-changer in the rapidly expanding AI chip market.

Currently, HBM chips are horizontally connected to the GPU on a silicon interposer using 2.5D packaging technology. In contrast, 3D packaging eliminates the need for a silicon interposer or thin substrates between chips, facilitating communication and collaborative operation. The 3D packaging approach reduces power consumption and processing latency while improving the quality of the electrical signals in semiconductor chips.

Samsung has named its new packaging technology SAINT-D, an acronym for Samsung Advanced Interconnect Technology - D.

The company will offer a turnkey 3D HBM packaging solution. Samsung's advanced packaging team will vertically interconnect HBM chips produced by its memory business division with GPUs assembled by its foundry division for fabless companies.

Looking ahead, Samsung plans to introduce an integrated heterogeneous technology by 2027, which will incorporate optical components capable of significantly increasing semiconductor data transfer speeds into a unified AI accelerator package. This move is expected to further cement Samsung's position at the forefront of semiconductor innovation and packaging technology.