Samsung Electronics, at its annual industry event, declared advancements in its manufacturing process with the introduction of two new state-of-the-art nodes, SF2Z and SF4U. The tech giant plans to integrate its storage chips, foundry, and packaging services to offer a streamlined, one-stop solution to customers, significantly reducing the total turnaround time by 20% and allowing for customization based on specific AI needs.

The newly announced 2nm process, SF2Z, incorporates an optimized Backside Power Delivery Network (BSPDN) technology, which positions power rails on the wafer's backside to eliminate bottlenecks between power and signal lines. This innovation promises enhanced power, performance, and area (PPA) as well as a notable reduction in voltage drop, boosting the performance of high-performance computing (HPC) designs. Mass production of SF2Z is expected to commence in 2027.

Additionally, the 4nm variant, SF4U, is slated for mass production in 2025, offering PPA improvements through optical scaling. Samsung also reaffirmed that preparations for the SF1.4 node are on track, with performance and yield targets anticipated to be met by 2027.

Samsung emphasized its commitment to advancing beyond Moore's Law through continuous innovation in materials and structures, actively shaping future process technologies below the 1.4-nanometer threshold.

The maturity of Samsung's Gate-All-Around (GAA) technology has been highlighted as a key driver for enabling artificial intelligence. As the GAA process enters its third year of mass production, it continues to demonstrate improvements in yield and performance. Leveraging its accumulated GAA production experience, Samsung plans to produce its second-generation 3nm process (SF3) in the second half of this year and will implement GAA in its upcoming 2nm process.

Since 2022, Samsung's GAA production yield has been steadily increasing and is expected to expand significantly in the coming years, marking a new era in AI chip manufacturing efficiency.