TSMC has announced delivery of the complete version of its 5nm design infrastructure within the Open Innovation Platform (OIP). This full release enables 5nm systems-on-chip (SoC) designs in next-generation advanced mobile and high-performance computing (HPC) applications, targeting high-growth 5G and artificial intelligence markets.

TSMC said leading EDA and IP vendors collaborated with it to develop and validate the complete design infrastructure, including technology files, process design kits (PDKs), tools, flows and IP, through multiple silicon test vehicles.

TSMC's 5nm process is already in risk production and offers IC designers a new level of performance and power optimization targeted at the next generation of high-end mobile and HPC applications. Compared with TSMC's 7nm process, its innovative scaling features deliver 1.8X logic density and 15% speed gain on an ARM Cortex-A72 core, along with superior SRAM and analog area reduction enabled by the process architecture, TSMC said. The 5nm process enjoys the benefits of process simplification provided by EUV lithography, and is making excellent progress in yield learning, achieving the best technology maturity at the same corresponding stage as compared to TSMC's previous nodes.

TSMC's comprehensive 5nm design infrastructure includes the full versions of the 5nm design rule manual (DRM), SPICE model, process design kits (PDKs) and silicon-validated foundation and interface IP, and also supports a full range of certified EDA tools and design flows. Backed by the resources of the largest design ecosystem in the industry, TSMC's OIP, customers have already started intensive design engagements, paving the way for product tape-outs, pilot activities and early sampling.

"TSMC's 5-nanometer technology offers our customers the industry's most advanced logic process to address the exponentially growing demand for computing power driven by AI and 5G," said Cliff Hou, VP of R&D and technology development at TSMC. "5-nanometer technology requires deeper design-technology co-optimization. Therefore, we collaborate seamlessly with our ecosystem partners to ensure we deliver silicon-validated IP blocks and EDA tools ready for customer use. As always, we are committed to helping customers achieve first-time silicon success and faster time-to-market."

TSMC collaborated with design ecosystem partners, including Cadence, Synopsys, Mentor Graphics, and ANSYS to certify full-line EDA tools through the TSMC OIP EDA Tool Certification Program.

The entire TSMC 5nm design infrastructure is available now from TSMC Online for customer downloads.