Packaging and testing firm Powertech Technology (PTI) expects the development of new technologies including wafer-level packaging, 3D IC packaging and copper pillar bumping to bear fruit in 2012-2013. The company also added that subsidiary Macrotech Technology will start running a new fab later in 2012, in preparation for commercial production of products built using these advanced packaging technologies.
Macrotech broke ground for the new fab located in Hsinchu, northern Taiwan, in March, PTI indicated. Trial production is slated to start in the third quarter of 2012, after equipment move-in is complete, PTI revealed.
PTI said that the company has been developing wafer-level packaging and advanced technologies such as through silicon via (TSV) and Si interposer packaging at its laboratory, which supports pilot plant operations, in Hsinchu for about a year.
The pilot plant lab was formerly a factory building owned by ProMOS Technologies, which used it as collateral for debts owed to Kingston Technology. PTI acquired the facility from Kingston for NT$1.178 billion in mid-2010.
PTI chairman DK Tsai previously remarked that the company aims to become the number-four IC packaging and testing house worldwide in three years. More than a year ago it set up a R&D team to focus on 3D IC technologies such as MCP, SiP and TSV packaging, with an aim to put a greater emphasis on non-memory products.
PTI specializes in backend services for memory ICs, with major clients including Elpida Memory and Toshiba.