The era of memory-dominated packaging technology has arrived, and heterogeneous stacking with memory and logic devices has become a trend, according to DK Tsai, chairman and CEO for Taiwan-based Powertech Technology (PTI).

As consumer technology products increasingly require thinner and lighter, high-performance and low-power memory devices, advanced packaging technologies including flip-chip (FC), bumping and fan-out have drawn much attention as popular solutions, said Tsai. These are also the areas PTI will be focusing on over the next two to three years, Tsai indicated.

Stacking of multiple memory chips on a processor chip can be realized through 3D FC or TSV technologies, which, however, are not cost competitive and create other challenges, Tsai said.

Meanwhile, the importance of wafer-level heterogeneous integration technologies has become significant, particularly in the artificial intelligence (AI) field, Tsai noted.

In addition, Tsai predicted that the supply of DRAM and NAND flash will remain short of demand in the second half of 2017. Tsai also expressed optimism about SSD demand which will drive NAND flash market growth.